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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18
18-Mbit QDRTM-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Functional Description
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs equipped with QDRTM-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus that is required with common IO devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched onto alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. In order to maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words (CY7C1163V18), or 36-bit words (CY7C1165V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K, memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the or K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Separate independent read and write data ports Supports concurrent transactions 300 MHz to 400 MHz clock for high bandwidth 4-word burst to reduce address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz Read latency of 2.5 clock cycles Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Single multiplexed address input bus latches address inputs for both read and write ports Separate port selects for depth expansion Data valid pin (QVLD) to indicate valid data on the output Synchronous internally self-timed writes Available in x8, x9, x18, and x36 configurations Full data coherency providing most current data Core VDD = 1.8V 0.1V; IO VDDQ = 1.4V to VDD[1] Available in 165-ball FBGA package (13 x 15 x 1.4 mm) Offered in both Pb-free and non Pb-free packages Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement

Configurations
With cycle read latency of 2.5 cycles: CY7C1161V18 - 2M x 8 CY7C1176V18 - 2M x 9 CY7C1163V18 - 1M x 18 CY7C1165V18 - 512K x 36
Selection Guide
400 MHz Maximum Operating Frequency Maximum Operating Current 400 1080 375 MHz 375 1020 333 MHz 333 920 300 MHz 300 850 Unit MHz mA
Note 1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation Document Number: 001-06582 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 15, 2007
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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18
Logic Block Diagram (CY7C1161V18)
D[7:0]
8
Write Reg Write Reg Write Reg Write Reg
Write Add. Decode
A(18:0)
19
Read Add. Decode
Address Register
Address Register
19
A(18:0)
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
K K
CLK Gen.
Control Logic
RPS
DOFF
Read Data Reg. 32 Control Logic 16 16 Reg. Reg. 8 Reg. 8
CQ CQ Q[7:0] QVLD
VREF WPS NWS[1:0]
Logic Block Diagram (CY7C1176V18)
D[8:0]
9
Write Reg Write Reg Write Reg Write Reg
Write Add. Decode
A(18:0)
19
Read Add. Decode
Address Register
Address Register
19
A(18:0)
512K x 9 Array
512K x 9 Array
512K x 9 Array
512K x 9 Array
K K
CLK Gen.
Control Logic
RPS
DOFF
Read Data Reg. 36 Control Logic 18 18 Reg. Reg. 9 Reg. 9
CQ CQ Q[8:0] QVLD
VREF WPS BWS[0]
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Logic Block Diagram (CY7C1163V18)
D[17:0]
18
Write Reg Write Reg Write Reg Write Reg
Write Add. Decode
A(17:0)
18
Read Add. Decode
Address Register
Address Register
18
A(17:0)
256K x 18 Array
256K x 18 Array
256K x 18 Array
256K x 18 Array
K K
CLK Gen.
Control Logic
RPS
DOFF
Read Data Reg. 72 Control Logic 36 36 Reg. Reg. 18 Reg. 18
CQ CQ Q[17:0]
VREF WPS BWS[1:0]
QVLD
Logic Block Diagram (CY7C1165V18)
D[35:0]
36
Write Reg Write Reg Write Reg Write Reg
Write Add. Decode
A(16:0)
17
Read Add. Decode
Address Register
Address Register
17
A(16:0)
128K x 36 Array
128K x 36 Array
128K x 36 Array
128K x 36 Array
K K
CLK Gen.
Control Logic
RPS
DOFF
VREF WPS BWS[3:0]
Read Data Reg. 144 Control Logic 72 72 Reg. Reg. 36 Reg. 36
CQ CQ Q[35:0]
QVLD
Document Number: 001-06582 Rev. *C
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Pin Configurations
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1161V18 (2M x 8)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3
A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC
7
NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11
CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CY7C1176V18 (2M x 9)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
NC/72M NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK
3
A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC
7
NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/36M NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS
11
CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
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Pin Configurations (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1163V18 (1M x 18)
1 A B C D E F G H J K L M N P R
CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO
2
Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3
D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC
7
NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
10
NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/144M NC/36M
CY7C1165V18 (512K x 36)
1 A B C D E F G H J K L M N P R
CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO
2
Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3
D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A
4
WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
5
BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
6
K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC
7
BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A
8
RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A
9
D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A
10
Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11
CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
NC/288M NC/72M
NC/36M NC/144M
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Pin Definitions
Pin Name D[x:0] IO Pin Description InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1161V18-D[7:0] CY7C1176V18-D[8:0] CY7C1163V18-D[17:0] CY7C1165V18-D[35:0] InputWrite Port Select - Active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes D[x:0] to be ignored. InputNibble Write Select 0, 1 - Active LOW (CY7C1161V18 Only). Sampled on the rising edge of the Synchronous K and K clocks during Write operations. Used to select the nibble that is written into the device. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select causes the corresponding nibble of data to be ignored and not written into the device. InputByte Write Select 0, 1, 2, and 3 - Active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. Used to select the byte that is written into the device during the current portion of the write operation. Bytes not written remain unaltered. CY7C1176V18 - BWS0 controls D[8:0]. CY7C1163V18 - BWS0 controls D[8:0] and BWS1 controls D[17:9].. CY7C1165V18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18], and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select causes the corresponding byte of data to be ignored and not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock duing active read and write operations. Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1161V18, 2M x 9 (4 arrays each of 512K x 9) for CY7C1176V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1163V18, and 512K x 36 (4 arrays each of 128K x 36) for CY7C1165V18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1161V18 and CY7C1176V18, 18 address inputs for CY7C1163V18, and 17 address inputs for CY7C1165V18. These inputs are ignored when the appropriate port is deselected. OutputsData Output Signals. These pins drive out the requested data during a read operation. Valid data Synchronous is driven out on the rising edge of both the K and K clocks during read operations or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated. CY7C1161V18 - Q[7:0]. CY7C1176V18 - Q[8:0]. CY7C1163V18 - Q[17:0]. CY7C1165V18 - Q[35:0]. InputRead Port Select - Active LOW. Sampled on the rising edge of positive input clock (K). When active, Synchronous a read operation is initiated. Deasserting causes the read port to be deselected. When deselected, the pending access is enabled to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. Valid Output Indicator InputClock InputClock Echo Clock Valid Output Indicator. Indicates valid output data. QVLD is edge-aligned with CQ and CQ. Positive Input Clock Input. Rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and to drive out data through Q[x:0] when in single clock mode. Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in "Switching Characteristics" on page 23.
WPS
NWS0, NWS1,
BWS0, BWS1, BWS2, BWS3
A
Q[x:0]
RPS
QVLD K
K CQ
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Pin Definitions (continued)
Pin Name CQ IO Echo Clock Pin Description Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timings for the echo clocks are shown in "Switching Characteristics" on page 23. Output Impedance Matching Input. Used to tune the device outputs to the system data bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off - Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned-off operation are different from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency of up to 167 MHz with QDR-I timing. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.
ZQ
Input
DOFF
Input
TDO TCK TDI TMS NC NC/36M NC/72M
Output Input Input Input N/A N/A N/A N/A N/A InputReference
NC/144M NC/288M
VREF VDD VSS VDDQ
Power Supply Power supply inputs to the core of the device. Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
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Functional Overview
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are synchronous pipelined burst SRAMs equipped with both a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to "turn-around" the data bus. It avoids any possible data contention, thereby, simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1161V18, four 9-bit data transfers in the case of CY7C1176V18, four 18-bit data transfers in the case of CY7C1163V18, and four 36-bit data transfers in the case of CY7C1165V18 in two clock cycles. Accesses for both ports are initiated on the positive input clock (K). All synchronous input and output timings are referenced to the rising edge of the Input clocks (K/K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the Input clocks (K and K) also. All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1163V18 is described in the following sections. The same basic descriptions apply to CY7C1161V18, CY7C1176V18, and CY7C1165V18.
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses are initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1163V18. A write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate byte write select input during the data portion of a write enables the data being presented to be latched and written into the device. Deasserting the byte write select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, and write operations to a byte write operation.
Read Operations
The CY7C1163V18 is organized internally as four arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to address inputs are stored in the Read address register. Following the next two K clock rises, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the Input clock K or K. In order to maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks K and K. When the read port is deselected, the CY7C1163V18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative input clock (K). This allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory.
Concurrent Transactions
The read and write ports on the CY7C1163V18 operate completely independent of one another. Because each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle initiated on the previous K clock rise. Read accesses and write access are scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read is initiated on the previous cycle, the write port assumes priority (because read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port assumes priority (because write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations initiated, with the first access being a read.
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Depth Expansion
The CY7C1163V18 has a port select input for each port. This enables easy depth expansion. Both port selects are only sampled on the rising edge of the positive input clock (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, "DLL Considerations in QDRII/DDRII/QDRII+/DDRII+." The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be reset in order to lock to the desired frequency. During power up when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks and are synchronized to the input clock of the QDR-II+. The timings for the echo clocks are shown in the AC timing table.
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Application Example
Figure 1 shows four QDR-II+ used in an application. Figure 1. Application Example
ZQ CQ/CQ SRAM #1 Q D A RPS WPS BWS K K RQ = 250ohms RQ = 250ohms
Vt R
D A
ZQ CQ/CQ SRAM #4 Q RPS WPS BWS K K
DATA IN DATA OUT Address
R R
Vt Vt
BUS MASTER RPS (CPU or ASIC) WPS
BWS CLKIN/CLKIN Source K Source K R = 50ohms, Vt = VDDQ /2
Truth Table
The truth table for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.[3, 4, 5, 6, 7, 8] Operation Write Cycle: Load address on rising edge of K; input write data on two consecutive K and K rising edges. Read Cycle (2.5 Cycle Latency): Load address on rising edge of K; wait one and a half cycle; read data on two consecutive K and K rising edges. NOP: No operation. Standby: Clock stopped. K L-H RPS WPS H[9] DQ DQ DQ DQ
L[10] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
L-H
L[10]
X
Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)
L-H Stopped
H X
H X
D=X Q = High Z Previous State
D=X Q = High Z Previous State
D=X Q = High Z Previous State
D=X Q = High Z Previous State
Notes 2. The above application shows four QDR-II+ being used. 3. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 4. Device powers up deselected and the outputs in a tri-state condition. 5. "A" represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst. 6. "t" represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, respectively succeeding the "t" clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges. 8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. If this signal was LOW to initiate the previous cycle, this signal becomes a "Don't Care" for this operation. 10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.
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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18
Write Cycle Descriptions
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.[3, 11] BWS0/ BWS1/ NWS0 L NWS1 L K L-H K - Comments During the data portion of a write sequence: CY7C1161V18 - both nibbles (D[7:0]) are written into the device. CY7C1163V18 - both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the data portion of a write sequence: CY7C1161V18 - both nibbles (D[7:0]) are written into the device. CY7C1163V18 - both bytes (D[17:0]) are written into the device. - During the data portion of a write sequence: CY7C1161V18 - only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1163V18 - only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L-H
L
H
-
L-H During the data portion of a write sequence: CY7C1161V18 - only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1163V18 - only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. - During the data portion of a write sequence: CY7C1161V18 - only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1163V18 - only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L-H
H
L
-
L-H During the data portion of a write sequence: CY7C1161V18 - only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1163V18 - only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. - No data is written into the device during this portion of a write operation. L-H No data is written into the device during this portion of a write operation.
H H
H H
L-H -
The write cycle operation of CY7C1176V18 follows.[3, 11] BWS0 L L H H K L-H - L-H - K - L-H - L-H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Note 11. Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a Write cycle, as long as the setup and hold requirements are achieved.
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The write cycle descriptions of CY7C1165V18 follows.[3, 11] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H - L-H - L-H - L-H - L-H - L-H - K - Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device.
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. - During thedata portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered.
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. - During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. - During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. - During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. - No data is written into the device during this portion of a write operation. L-H No data is written into the device during this portion of a write operation.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard 1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels.
Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in "TAP Controller Block Diagram" on page 16. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The "Boundary Scan Order" on page 19 show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSb of the register is connected to TDI and the LSb is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the "Identification Register Definitions" on page 18.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state which does not interfere with the operation of the device.
Test Access Port--Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see "TAP Controller State Diagram" on page 15 TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSb) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine, see "Instruction Codes" on page 18 The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSb) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the "Instruction Codes" on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and enables data to be scanned into and out of the SRAM test circuitry. Only one register is selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data outputs on the TDO pin on the falling edge of TCK.
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IDCODE The IDCODE instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP then tries to capture a signal while in transition (metastable state). This does not harm the device but there is no guarantee as to the value that is captured. Repeatable results are not possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal is stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input is not captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data is shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller puts the output bus into a tri-state mode. The boundary scan register has a special bit located at bit 47. When this scan cell, called the "extest output bus tri-state", is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High Z condition. This bit is set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test Logic Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram
Figure 2. Tap Controller State Diagram[12]
1
TEST-LOGIC RESET 0 1
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
1
SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram
Figure 3. Tap Controller Block Diagram
0 Bypass Register TDI Selection Circuitry 2 Instruction Register 31 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 106 . . . . 2 1 0 Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics
The Tap Electrical Characteristics table over the operating range follows.[13, 14, 15] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDD Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A -0.3 -5 Min 1.4 1.6 0.4 0.2 0.65 VDD VDD + 0.3 0.35 VDD 5 Max Unit V V V V V V A
Notes 13. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 14. Overshoot: VIH(AC) < VDDQ + 0.35V (pulse width less than tCYC/2), Undershoot: VIL(AC) > -0.3V (pulse width less than tCYC/2) 15. All voltage referenced to ground.
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TAP AC Switching Characteristics
The Tap AC Switching Characteristics over the operating range follows.[16, 17] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns
TAP Timing and Test Conditions
The Tap Timing and Test Conditions for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.[17]
0.9V 50 TDO Z0 = 50 0V CL = 20 pF ALL INPUT PULSES 1.8V 0.9V
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data In TDI
Test Data Out TDO
tTDOV tTDOX
Notes 16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 17. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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Identification Register Definitions
Instruction Field Revision Number (31:29) Value CY7C1161V18 000 CY7C1176V18 000 CY7C1163V18 000 CY7C1165V18 000 Description Version number.
Cypress Device ID 11010010001000101 11010010001001101 11010010001010101 11010010001100101 Defines the type of (28:12) SRAM. Cypress JEDEC ID (11:1) ID Register Presence (0) 00000110100 00000110100 00000110100 00000110100 Enables unique identification of SRAM vendor. Indicates the presence of an ID register.
1
1
1
1
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 107
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. This forces all SRAM output drivers to a High Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. This operation does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
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Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Bump ID 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A Bit # 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Bump ID 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F Bit # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Bump ID 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
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Power Up Sequence in QDR-II+ SRA
During power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. .QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
DLL Constraints

DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var The DLL functions at frequencies down to 120 MHz If the input clock is unstable and the DLL is enabled, then the DLL locks onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency
Power Up Sequence
Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) -- Apply VDD before VDDQ -- Apply VDDQ before VREF or at the same time as VREF
Provide stable power and clock (K, K) for 2048 cycles to lock the DLL
Power Up Waveforms
Figure 4. Power Up Waveforms
K K
~ ~
Unstable Clock > 2048 Stable Clock Start Normal Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)
VDD/VDDQ
VDD/VDDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to VDDQ)
DOFF
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied. -55C to + 125C Supply Voltage on VDD Relative to GND .......-0.5V to + 2.9V Supply Voltage on VDDQ Relative to GND ..... -0.5V to + VDD DC Applied to Outputs in High Z ........ -0.5V to VDDQ + 0.3V DC Input Voltage[14] ............................... -0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature (TA) 0C to +70C -40C to +85C VDD[18] 1.8 0.1V VDDQ[18] 1.4V to VDD
Electrical Characteristics
The DC Electrical Characteristics over the operating range follows.[15] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Input Reference Voltage[21] VDD Operating Supply GND VI VDDQ GND VI VDDQ, Output Disabled Typical Value = 0.75V VDD = Max, IOUT = 0 mA, 300 MHz f = fmax = 1/tCYC 333 MHz 375 MHz 400 MHz ISB1 Automatic Power Down Current Max VDD, Both Ports Deselected, VIN VIH or VIN VIL f = fmax = 1/tCYC, Inputs Static 300 MHz 333 MHz 375 MHz 400 MHz Note 19 Note 20 IOH = -0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min 1.7 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.15 -2 -2 0.68 0.75 Typ 1.8 1.5 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.15 VREF - 0.1 2 2 0.95 850 920 1020 1080 250 260 290 300 Unit V V V V V V V V A A V mA mA mA mA mA mA mA mA
AC Electrical Characteristics
Over the operating range follows.[21] Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min VREF + 0.2 -0.24 Typ - - Max VDDQ + 0.24 VREF - 0.2 Unit V V
Notes 18. Power up: Is based upon a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 19. Output are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 21. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max 5 6 7 Unit pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 17.2 4.15 Unit C/W C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[22]
ZQ
(a)
RQ = 250
INCLUDING JIG AND SCOPE
RQ = 250 (b)
Notes 22. Unless otherwise noted, test conditions are based upon signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
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Switching Characteristics
Over the operating range[22, 23] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH Description VDD(Typical) to the First Access[24] K Clock Cycle Time Input Clock (K/K) HIGH Input Clock (K/K) LOW K Clock Rise to K Clock Rise (rising edge to rising edge) Address Setup to K Clock Rise Control Setup to K Clock Rise (RPS, WPS) 400 MHz 1 0.4 0.4 1.06 - - - - 375 MHz 1 0.4 0.4 1.13 - - - - 333 MHz 1 3.0 0.4 0.4 1.28 - 8.40 - - - 300 MHz 1 3.3 0.4 0.4 1.40 - 8.40 - - - Min Max Min Max Min Max Min Max 2.50 8.40 2.66 8.40 Unit ms ns tCYC tCYC ns
Setup Times tSA tSC tSCDDR tSD tHA tHC tHCDDR tHD tCO tDOH tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tQVLD tAVKH tIVKH tIVKH tDVKH tKHAX tKHIX tKHIX tKHDX tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ tCHQX1 tQVLD 0.4 0.4 - - - - - - - - 0.45 - 0.45 - 0.2 - - - 0.45 - -0.2 0.88 0.88 - -0.45 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 - -0.45 - -0.45 - - - - - - - - 0.45 - 0.45 - 0.2 - - - 0.45 - -0.2 1.03 1.03 - -0.45 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 - -0.45 - -0.45 - - - - - - - - 0.45 - 0.45 - 0.2 - - - 0.45 - -0.2 1.15 1.15 - -0.45 0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28 - -0.45 - -0.45 - - - - - - - - 0.45 - 0.45 - 0.2 - - - 0.45 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Double Data Rate Control Setup to Clock (K, K) 0.28 Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Setup to Clock (K/K) Rise Address Hold after K Clock Rise Control Hold after K Clock Rise (RPS, WPS) 0.28 0.4 0.4
Hold Times
Double Data Rate Control Hold after Clock (K/K) 0.28 Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise K/K Clock Rise to Data Valid Data Output Hold after Output K/K Clock Rise (Active to Active) K/K Clock Rise to Echo Clock Valid Echo Clock Hold after K/K Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Output Clock (CQ/CQ) HIGH CQ Clock Rise to CQ Clock (rising edge to rising edge) Clock (K/K) Rise to Low
[25]
0.28 - -0.45 - -0.45 - -0.2 0.81 0.81 - -0.45
Output Times
Rise[25]
Clock (K/K) Rise to High Z (Active to High Z)[26, 27] Z[26, 27] Valid[28] Echo Clock High to QVLD
-0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20
Notes 23. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 24. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated. 25. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production. 26. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady state voltage. 27. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 28. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
Document Number: 001-06582 Rev. *C
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Switching Characteristics
Over the operating range[22, 23] (continued) Cypress Consortium Parameter Parameter DLL Timing tKC Var tKC lock tKC Reset tKC Var tKC lock tKC Reset Clock Phase Jitter DLL Lock Time (K) K Static to DLL Reset[29] - 2048 30 0.20 - - - 2048 30 0.20 - - - 2048 30 0.20 - - - 2048 30 0.20 - - ns Cycles ns Description 400 MHz 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max Min Max Unit
Note 29. Hold to >VIH or Document Number: 001-06582 Rev. *C
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Switching Waveforms Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency[30, 31, 32]
NOP 1
K
t KH t KL
READ 2
t CYC
WRITE 3
t KHKH
READ 4
WRITE 5
NOP 6
7
8
K RPS
t SC tHC t SC t HC
WPS A
t SA A0 t HA t SD A1 t HD D10 t QVLD t CLZ
t
A2
A3 t HD D13 D30 D31 D32 D33 tQVLD tDOH tCQD Q01 Q02 Q03 Q20 tCQDOH
t SD D11 D12
D QVLD
CO Q00
tCHZ Q23
Q
(Read Latency = 2.5 Cycles) tCQOH
Q21
Q22
tCCQO
CQ
t CQH t CQHCQH tCQOH
t CCQO
CQ
DON'T CARE
UNDEFINED
Notes 30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1. 31. Outputs are disabled (High Z) one clock cycle after a NOP. 32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-06582 Rev. *C
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Ordering Information
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 400 Ordering Code CY7C1161V18-400BZC CY7C1176V18-400BZC CY7C1163V18-400BZC CY7C1165V18-400BZC CY7C1161V18-400BZXC CY7C1176V18-400BZXC CY7C1163V18-400BZXC CY7C1165V18-400BZXC CY7C1161V18-400BZI CY7C1176V18-400BZI CY7C1163V18-400BZI CY7C1165V18-400BZI CY7C1161V18-400BZXI CY7C1176V18-400BZXI CY7C1163V18-400BZXI CY7C1165V18-400BZXI 375 CY7C1161V18-375BZC CY7C1176V18-375BZC CY7C1163V18-375BZC CY7C1165V18-375BZC CY7C1161V18-375BZXC CY7C1176V18-375BZXC CY7C1163V18-375BZXC CY7C1165V18-375BZXC CY7C1161V18-375BZI CY7C1176V18-375BZI CY7C1163V18-375BZI CY7C1165V18-375BZI CY7C1161V18-375BZXI CY7C1176V18-375BZXI CY7C1163V18-375BZXI CY7C1165V18-375BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Package Diagram Package Type Operating Range Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Document Number: 001-06582 Rev. *C
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Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 333 Ordering Code CY7C1161V18-333BZC CY7C1176V18-333BZC CY7C1163V18-333BZC CY7C1165V18-333BZC CY7C1161V18-333BZXC CY7C1176V18-333BZXC CY7C1163V18-333BZXC CY7C1165V18-333BZXC CY7C1161V18-333BZI CY7C1176V18-333BZI CY7C1163V18-333BZI CY7C1165V18-333BZI CY7C1161V18-333BZXI CY7C1176V18-333BZXI CY7C1163V18-333BZXI CY7C1165V18-333BZXI 300 CY7C1161V18-300BZC CY7C1176V18-300BZC CY7C1163V18-300BZC CY7C1165V18-300BZC CY7C1161V18-300BZXC CY7C1176V18-300BZXC CY7C1163V18-300BZXC CY7C1165V18-300BZXC CY7C1161V18-300BZI CY7C1176V18-300BZI CY7C1163V18-300BZI CY7C1165V18-300BZI CY7C1161V18-300BZXI CY7C1176V18-300BZXI CY7C1163V18-300BZXI CY7C1165V18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Package Diagram Package Type Operating Range Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Document Number: 001-06582 Rev. *C
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Package Diagram
Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
BOTTOM VIEW PIN 1 CORNER TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B O0.50 -0.06 (165X)
+0.14 4 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 3 2 1 A B
1 A B
2
1.00
C D E F G
C D E F G
15.000.10
15.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A
A 5.00 10.00 B 13.000.10 B 0.15(4X) 13.000.10
1.00
1.40 MAX.
NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC
0.530.05
0.25 C
SEATING PLANE 0.36 C 0.350.06
0.15 C
51-85180-*A
Document Number: 001-06582 Rev. *C
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Document History Page
Document Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/CY7C1165V18, 18-Mbit QDRTM-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-06582 REV. ** *A ECN No. 430351 461654 Issue Date See ECN See ECN Orig. of Change NXR NXR New data sheet Revised the MPNs from CY7C1176BV18 to CY7C1176V18 CY7C1163BV18 to CY7C1163V18 CY7C1165BV18 to CY7C1165V18 Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified power up waveform Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in Operating Range table and in the DC Electrical Characteristics table Added foot note in page 1 Changed the Maximum rating of Ambient Temperature with Power Applied from -10C to +85C to -55C to +125C Changed VREF (max) spec from 0.85V to 0.95V in the DC Electrical Characteristics table and in the note below the table Updated foot note 22 to specify Overshoot and Undershoot Spec Updated JA and JC values Removed x9 part and its related information Updated footnote 25 Description of Change
*B
497629
See ECN
NXR
*C
1167806
See ECN VKN/KKVTMP Converted from preliminary to final Added x8 and x9 parts Changed IDD values from 800 mA to 1080 mA for 400 MHz, 766 mA to 1020 mA for 375 MHz, 708 mA to 920 mA for 333 MHz, 663 mA to 850 mA for 300 MHz Changed ISB values from 235 mA to 300 mA for 400 MHz, 227 mA to 290 mA for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz Changed tCYC(max) spec to 8.4 ns for all speed bins Changed JA value from 13.48 C/W to 17.2 C/W Updated Ordering Information table
(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06582 Rev. *C
Revised June 15, 2007
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QDRTM is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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